Need help setting up my Milk-V Megrez, where can I find a working software image?

I bought a Milk-V Megrez and wanted to use it like a simple desktop PC. I was aware that this board is very experimental and of course there isn't really much support, especially when it comes to the software, but what I didn't think was that it would be so difficult to get a halfway decent image at all. I thought that if Deepin, Ubuntu, Fedora, and Debian were printed in bold on the packaging, they must at least be available in a modified version. Well, I was wrong.

I first tried the links on the manufacturer's website. They offer a modified Fedora and Debian, or rather, Rockos. So far, so good. Unfortunately, the link for Fedora doesn't lead anywhere, or the website can't be displayed. Rockos takes me to a GitHub page. When I download the image, I can't unpack the file because it's supposedly corrupted.

Now I've taken a look at the Deepin project. The website is, of course, entirely in Chinese, but the file is also in a completely strange format.

Then I looked into Bainbu and was able to download an IMG file for the first time, hoping that it might actually run. I then used the BalenaEtcher program to write to the micro SD card, as recommended on the website.The SD card was no longer recognized, either on my Mac or on the RISC board.

The EFI (or whatever the chip's program is called) only attempts to boot something, which fails. I can't write anything there because apparently the wireless keyboard isn't recognized either.

Do any of you have a bit more experience than me and can help me with this? I'd just install Linux for now, preferably an older image if there's nothing more recent. I don't care about the distribution.

I thought it worked similarly to ARM boards, like the Raspberry Pi or the Pine64. Am I completely wrong?

https://redd.it/1khmnea
@r_riscv

What architectures to target?

rustc supports so many options:

riscv32-wrs-vxworks
riscv32e-unknown-none-elf
riscv32em-unknown-none-elf
riscv32emc-unknown-none-elf
riscv32gc-unknown-linux-gnu
riscv32gc-unknown-linux-musl
riscv32i-unknown-none-elf
riscv32im-risc0-zkvm-elf
riscv32im-unknown-none-elf
riscv32ima-unknown-none-elf
riscv32imac-esp-espidf
riscv32imac-unknown-none-elf
riscv32imac-unknown-nuttx-elf
riscv32imac-unknown-xous-elf
riscv32imafc-esp-espidf
riscv32imafc-unknown-none-elf
riscv32imafc-unknown-nuttx-elf
riscv32imc-esp-espidf
riscv32imc-unknown-none-elf
riscv32imc-unknown-nuttx-elf
riscv64-linux-android
riscv64-wrs-vxworks
riscv64gc-unknown-freebsd
riscv64gc-unknown-fuchsia
riscv64gc-unknown-hermit
riscv64gc-unknown-linux-gnu
riscv64gc-unknown-linux-musl
riscv64gc-unknown-netbsd
riscv64gc-unknown-none-elf
riscv64gc-unknown-nuttx-elf
riscv64gc-unknown-openbsd
riscv64imac-unknown-none-elf
riscv64imac-unknown-nuttx-elf

For a random tiny Python package someone may want to pull from PYPI, what architectures should I realistically support or publish for?

Thanks and sorry for a noob question.

https://redd.it/1kicnof
@r_riscv

DC-Roma 8 core P550 mainboard for Frame laptop
https://deepcomputing.io/product/dc-roma-risc-v-ai-pc/

https://redd.it/1kin6qb
@r_riscv

Kaleidoscopico - 17000 lines of RISC-V assembler (demo)
https://www.youtube.com/watch?v=KhhLoVBpg48

https://redd.it/1kirnsh
@r_riscv

What happened to the zbp instruction set?

Back in 2021 or so, the bitmanip extension draft included a number of really powerful and general operations (grev, gorl etc) that if I understand correctly got moved to a "zbp" extension when bitmanip got split up. From then, as far as I can tell, nothing happened with ratifying zbp.

Is this more or less correct? Is there a plan to ratify it eventually or is it just outdated?

https://redd.it/1kj0xxo
@r_riscv

Milk-V Showcases Jupiter NX, a RISC-V-Based Alternative to Jetson Nano Modules
https://linuxgizmos.com/milk-v-showcases-jupiter-nx-a-risc-v-based-alternative-to-jetson-nano-modules/

https://redd.it/1kj2lwl
@r_riscv

Unboxing SpacemiT MUSE Pi Pro RISC-V SBC

Disclosure: SpacemiT sent me the MUSE Pi Pro RISC-V SBC for free

As it is has the same SpacemiT K1 as the Banana Pi BPI-F3, no surprises here.

The Bianbu image has limited support for the GPU, mpv can use the VPU for hardware video decoding and it comes with a front-end for some AI programs (Ollama, Yolo, etc.).

I also did some quick tests with Box64 and Docker.

https://youtu.be/1OsPdJXyRak

They shipped it without a cooler, and pushing the 8 CPU cores to 100% will get it to 95 degrees Celsius in a couple of minutes, locking up the board. Adding a fan will prevent this.

For anyone interested, here is the unboxing: https://youtu.be/1CzznQ4gntA

Developer: https://developer.spacemit.com
Forum: https://forum.spacemit.com

https://redd.it/1kj6wvw
@r_riscv

Codasip introduces L150 32-bit 3-stage core focused on customization
https://codasip.com/2025/05/08/bounded-customization-in-action-codasip-l150-and-cordic-acceleration-for-motor-control/

https://redd.it/1kj9b4h
@r_riscv

Problems adding custom instruction to riscv vector extension in qemu

As stated in the title I want to add a new instruction. It is similar to vfmacc.vv but it is called mfmacc.vv and treats the vectors registers as matrix. I have added the instruction to riscv-opcode and riscv-gnu-toolchain. I wrote a simple program to test if its compiles, it does, with no problem. Then i added the instruction in qemu. Currently it is just vfmacc with another name. When triying to execute it in qemu i come accross the following message: "Illegal instruction (core dumped)". I tried the exact same code with vfmacc and it works.

The changes i conduct in qemu file are:
riscv/insn\_trans/trans\_rvv.c.inc:

GEN_OPFVV_TRANS(mfmacc_vv, opfvv_check)

riscv/helper.h

/*Matrix operation*/
DEF_HELPER_6(mfmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(mfmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(mfmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32)

riscv/insn32.decode

mfmacc_vv 001011 . ..... ..... 001 ..... 1010111 @r_vm

funct6 is 001011 because it does not collide with the rest of vector instructions. And the rest is copied from vfmacc and correspond to the category OPFVV. The following link shows the OPCODE for vector arithmetic instructions and the funct3 for OPFVV.

[https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#sec-arithmetic-encoding](https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#sec-arithmetic-encoding)

riscv/vector\_helper.c

RVVCALL(OPFVV3, mfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
RVVCALL(OPFVV3, mfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
RVVCALL(OPFVV3, mfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
GEN_VEXT_VV_ENV(mfmacc_vv_h, 2)
GEN_VEXT_VV_ENV(mfmacc_vv_w, 4)
GEN_VEXT_VV_ENV(mfmacc_vv_d, 8)

You can check part of the decoded binary:

10248: 0d2672d7 vsetvli t0,a2,e32,m4,ta,ma
1024c: 0207e807 vle32.v v16,(a5)
10250: 02076a07 vle32.v v20,(a4)
10254: 0206ec07 vle32.v v24,(a3)
10258: 2f8a1857 mfmacc.vv v16,v20,v24
1025c: 0207e827 vse32.v v16,(a5)

And the command i use to execute it is:

/usr/local/bin/qemu-riscv64 -cpu rv64,v=true,vlen=128,elen=64,vext_spec=v1.0 simple_matrix

https://redd.it/1kja532
@r_riscv

Preparing for RISC-V Foundational Associate (RVFA) by Linux Foundation

Hey everyone,

I've always had a keen interest in CPU architecture. While I haven’t deeply explored x86 or ARM, I’ve picked up enough to help me with some reverse engineering tasks. Now, I really want to dive deep and properly learn a CPU architecture, firmware etc.

I’ve chosen RISC-V because of its open nature, and I genuinely believe it has a strong future. I want to contribute to that future in some way.

Right now, I’m going through the RISC-V Fundamentals (LFD210) course. But to be honest, the exam is just an excuse. I want to really understand the concepts and get my hands on it.

Please let me know if you have any suggestions that could help me in this journey.

Thanks in advance!

https://redd.it/1kjlgol
@r_riscv

Custom Instruction Opcode Format

I'm having trouble finding a comprehensive description of how to encode/decode custom instructions in the official RISC-V docs or repos.

The opcode table shows :

https://preview.redd.it/4ef6jy09x50f1.png?width=931&format=png&auto=webp&s=bfe664d916a9b8f58f3c0e3a88fcf3b432dea4f7

\- First of all, I'm guessing SYSTEM is `b1110011 - but I could not find it explicitly stated in the above section, so I worked back from other instructions like MRET that also use SYSTEM.

\- I assume I can set bits 25:15 and 11:7 to anything? (e.g immediate value or register select?)

\- (func3 == 0) and (func16 & `b1000111 == `b100011) differentiates custom instructions from other SYSTEM instructions?

I don't think any custom opcodes are defined in the standard machine readable specifications. Are there any good forks that have custom instructions?
(e.g https://github.com/riscv/riscv-opcodes or https://github.com/riscv/sail-riscv )

(I was collecting machine readable specs here https://www.five-embeddev.com/quickref/machine-readable.html and could not find any other examples - are there any good machine readable references for custom opcodes?)



https://redd.it/1kk2grr
@r_riscv

Best video tutorials to learn how to use Ripes (for Computer Engineering)

Hi everyone,
I'm a computer engineering student and I recently came across Ripes, the RISC-V visual pipeline simulator. I'm really interested in understanding how it works and how to use it effectively for learning CPU architecture and instruction pipelines.

Could anyone recommend good video tutorials or YouTube channels that explain Ripes clearly, especially from a computer engineering or academic perspective?

Also, if you’ve used it for coursework or learning purposes, I’d appreciate any tips or resources you found useful.

Thanks in advance!

https://redd.it/1kk5vj2
@r_riscv

Orange Pi RV2: Low-Cost RISC-V SBC | ExplainingComputers
https://www.youtube.com/watch?v=Mln2j3VxAos

https://redd.it/1kk7z5e
@r_riscv

Can MTIME and MTIMECMP be implemented as CSR-S?

Hello, currently i am working on implementing mtime and mtimecmp registers. My design is basic 32-bit, only machine mode, 1 core (basic structure). My idea was to use MCYCLE/H`s counter but this idea died the moment i learnt what MCOUNTINHIBIT is :). So is it possible to make them both csr-s?

https://redd.it/1kkaape
@r_riscv

Is there any board or chip available or announced that contain SiFive P870-A cores?



https://redd.it/1kkahnf
@r_riscv

Joining the Community. Looking for Resources

Hello!
I'm working on my project vm-kit

I am in need of some resources to get me going in the direction of creating a type-1 hypervisor on risc-v. I have found the rust crate for riscv (i plan to do this in rust). and found the opensbi for riscv, which might be necessary

I am looking for a much better understanding of configuring pmp and anything else I would need to know to accomplish this task.

I'm sure I'll have more posts and questions. Any resources you all used?
So far, i have found hypervisor from scratch part 1

https://redd.it/1kkaj9p
@r_riscv

Use of the RISC-V instruction set only in a Open-source FPGA design (license question)

I have started to create a VHDL design for new architecture. Now I'm thinking about the used instruction set. Could create an own encoding of the used machine code, but must create a C compiler for it or port the architecture to an existing compiler like GCC. Also must write an assembler, if I use an own instruction set.


What are the license requirements for me as developer, when I want use any specific parts of the RISC-V instruction set only? Would also to add some specific processor control registers and a modified base architecture. Might be security by obscurity, but control registers where I can setup the end of the stack and the size in privileged mode. Also two types of the stack. Return address and data, both separately as example.


BTW: The project is currently for the purpose of education only. Without interest from me to sell this maybe exotic (not RISC-V itself, but my modifications) architecture.




https://redd.it/1kkd6me
@r_riscv

Milk-V Megrez trouble with The bootloader

I wanted to get in touch again about my Milk-V Megrez.

First of all, the start of the image of Rockos worked very well in the end. I've never had it before that I unzip an image over several zip files, so I was overwhelmed at first. Actually, I should have read it better. I was able to start the system well and also Internet via cable works. The WLAN stick from me could also be set up, so far so good.

My bigger problem is that I had now tried to install Fedora (I didn't think anything would break). I had looked to the instructions and made the settings on Uboot (probably not quite right). Now Uboot has crashed and I can't restart the computer, no matter which image I use (Neither Rockos or Fedora can boot via the SD card). I'm really clumsy and don't know if I can heal it again.

I have now seen that I could save the whole thing over a UART/USB cable. (Updating/Re-Flashing U-Boot When U-Boot is Available)

https://milkv.io/docs/megrez/getting-started/boot

I hope I understand that correctly:

1. ⁠The board must be switched to recovery mode (the small unswitch at the top).
2. ⁠I simply pack the file "bootloader_milkv-megrez-2025-0224.bin" on a USB stick with EXT4 file format and plug it into any USB slot.
3. ⁠I plug the UART/USB cable into the board and into any other PC. When I turn on the board afterwards, the drive appears as "ESWIN-2030".

I have this information now from Gemini:

4. On the PC I can write down the path where the cable is listed via the Linux terminal with the command "dmesg | grep tty". I can then, when I have installed Minicon, simply open the configuration menu in the terminal "sudo minicom -s /dev/ttyUSB0 (customize path accordingly).

5. I select "Serial port setup". Then I give the path to the serial device (but here I wonder why I have to do this twice). Than I set the baud rate to „115200“. Data bits to „8“, the parity to „N“ (None) and the stop bits to „1“.

6. I choose "Save setup as dfl" to save the settings as default and leave the configuration menu again with "Exit".

7. I press Ctrl + A and then Q to finish.

I have no idea how the board behaves, whether it switches itself off or I can take it off the power. It should then work again after I have switched the recovery mode back to normal.

I now assume that this can also work easily via the Linux terminal of my Raspberry Pi.

I have seen this on Amazon. Do you think it can be work? https://amzn.eu/d/e68hL7

Did I understand the whole thing correctly? Have any of you had experience with this? Is there perhaps a much easier way that I am currently overseeing?

Many thanks for your help! <3

Sorry. Unfortunately, I'm pretty clueless. :-/

https://redd.it/1kkmzuj
@r_riscv

Support For New RISC-V SiFive Vendor Extensions On The Way For Linux 6.16
https://www.phoronix.com/news/Linux-6.16-New-SiFive-RISC-ISA

https://redd.it/1kko3z6
@r_riscv

Memory Mapped IO

I designed a memory mapped rv32 core with a simple memory controller and UART peripheral.

The thing confusing me is that should i set a "UART start transmit" bit in control register or i use "memory write" signal which generated by "S-Type instruction" for start transmitting?

Thank you!

https://redd.it/1kky9wl
@r_riscv